Clock circuit

ABSTRACT

The present invention provides a clock circuit comprises an oscillator circuit and a power-on reset circuit, the oscillator circuit comprises a current generating module and a loop oscillation module connected together; the current generating module is used for outputting a control current to the loop oscillation module; the loop oscillation module is used for outputting an oscillation signal with a set frequency under action of the control current; and the power-on reset circuit is used for providing an enabling control signal to the loop oscillation module after a power supply is powered on; the power-on reset circuit is connected to the loop oscillation module. In the present invention, the power-on reset circuit is only connected with the loop oscillation module, thus during a power-on process of the power supply, all nodes of the current generating module are gradually set with power-on of the power supply, thus a circuit setting time of the current generating module are comprised in a time for releasing an enable control signal of the power-on reset circuit, so as to accelerate a settling time of the oscillator circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority of International Patent ApplicationSerial No. PCT/CN2020/138331, filed Dec. 22, 2020, which is related toand claims priority of Chinese Patent Application Serial No.CN202010255345.7, filed Apr. 2, 2020. The entirety of each of theabove-mentioned patent applications is hereby incorporated herein byreference and made a part of this specification.

TECHNICAL FIELD

The disclosure relates to the technical field of integrated circuits, inparticular to a clock circuit.

BACKGROUND

With development of integrated circuits, circuit performances need to becontinuously improved, wherein, for an integrated circuit system, aclock circuit is an important input signal of many analog circuits anddigital circuits, thus the clock circuit is an important circuit in theintegrated circuits.

In many systems, the clock circuit must respond quickly after power-up,which can shorten a power supply-up settling time of an entire system.Therefore, how to start the clock circuit quickly and stably is animportant issue in the clock circuit. However, since an oscillatorcircuit in the clock circuit is controlled by a POR (Power-on Reset)circuit, voltages of all nodes of the entire oscillator circuit need tobe turned on simultaneously and slowly set until stable. As shown inFIG. 1 , the POR circuit of the clock circuit is connected to a currentgenerating module 10 and a loop oscillation module 20 simultaneously,thus the voltages of all nodes of the entire oscillator circuit need tobe set after releasing a control signal of the POR circuit, and then aclock can be stable only after the voltages of all nodes are stable. Itcauses a stabilization time of the oscillator circuit is a sum of a timefor releasing the POR circuit and a time required for stabilizing thevoltages of all of the nodes, thus an entire settling time is longer,and ultimately the entire oscillator circuit is set up slowly.

SUMMARY

The purpose of the present invention is to provide a clock circuit, tosolve a problem of slow setting of an oscillator circuit.

In order to achieve the above objective, the present invention providesa clock circuit comprises an oscillator circuit and a power-on resetcircuit, wherein the oscillator circuit comprises a current generatingmodule and a loop oscillation module connected together;

-   -   the current generating module is used for outputting a control        current to the loop oscillation module;    -   the loop oscillation module is used for outputting an        oscillation signal with a set frequency under action of the        control current; and    -   the power-on reset circuit is used for providing an enabling        control signal to the loop oscillation module after a power        supply is powered on;    -   the power-on reset circuit is connected to the loop oscillation        module.

Further, the loop oscillation module comprises a first sub-module and asecond sub-module, the first sub-module and the second sub-module areconnected in series, and the first sub-module comprises a plurality ofcomparators and control logic circuits.

Further, the first sub-module comprises a first comparator, a secondcomparator, a first control logic circuit and a second control logiccircuit;

-   -   a first input end of the first comparator is simultaneously        connected to a current mirror circuit branch and a second input        end of the second comparator; a second input end of the first        comparator is floating; a first input end of the first control        logic circuit is connected to an output end of the first        comparator; a second input end of the first control logic        circuit is connected to an output end of the second control        logic circuit; an output end of the first control logic circuit        is simultaneously connected to a switch control module and the        first input end of the second control logic circuit; a first        input end of the second comparator is floating, and an output        end of the second comparator is connected to a second input end        of the second control logic circuit.

Further, the power-on reset circuit comprises a first output end and asecond output end;

-   -   the first output end of the power-on reset circuit is        simultaneously connected to the first input end of the first        control logic circuit and the output end of the first        comparator; and the second output end of the power-on reset        circuit is simultaneously connected to the output end of the        second comparator and the second input end of the second control        logic circuit.

Further, the oscillator circuit further comprises the switch controlmodule, and the power-on reset circuit is connected to the looposcillation module by the switch control module.

Further, the switch control module is connected between the firstsub-module and the second sub-module.

Further, the switch control module comprises a first switch and a secondswitch;

-   -   a first end of the first switch is simultaneously connected to        the output end of the first control logic circuit and the        power-on reset circuit; a second end of the first switch is        simultaneously connected to a first end of the second switch and        the input end of the second sub-module; a second end of the        second switch is grounded and connected to the power-on reset        circuit simultaneously;    -   wherein, the first switch and the second switch are selectively        turned on.

Further, a first end of the second sub-module is connected to the switchcontrol module, and a second end of the second sub-module is connectedto the current mirror branch circuit and used as an output end of theoscillator circuit.

Further, the second sub-module comprises a plurality of inverters.

Further, the current generating module comprises a current mirrorcircuit branch, a feedback loop and a capacitor, the feedback loop isused for generating a substantially constant current required in theoscillator circuit, and the current mirror branch circuit is used forgenerating a current required for charging and discharging of theoscillator circuit and generating a periodic oscillation signal bycharging and discharging of the capacitor.

Comparing with the prior art, beneficial effects of the presentinvention are as following:

-   -   the present invention is to provide a clock circuit comprises an        oscillator circuit and a power-on reset circuit, the oscillator        circuit comprises a current generating module and a loop        oscillation module connected together; the current generating        module is used for outputting a control current to the loop        oscillation module; the loop oscillation module is used for        outputting an oscillation signal with a set frequency under        action of the control current; and the power-on reset circuit is        used for providing an enabling control signal to the loop        oscillation module after a power supply is powered on; the        power-on reset circuit is connected to the loop oscillation        module. In the present invention, the power-on reset circuit is        only connected with the loop oscillation module, thus during a        power-on process of the power supply, all nodes of the current        generating module are gradually set with power-on of the power        supply, thus a circuit setting time of the current generating        module are comprised in a time for releasing an enable control        signal of the power-on reset circuit, so as to accelerate a        settling time of the oscillator circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a clock circuit;

FIG. 2 is a schematic structural diagram of a clock circuit according toembodiment 1 of the present invention;

FIG. 3 is a schematic structural diagram of a clock circuit according toembodiment 2 of the present invention.

description of reference numbers:

in FIG. 1 :

-   -   10—current generating module; 20—loop oscillation module;

In FIGS. 2 and 3 :

-   -   C—capacitor; OTA—amplifier; M0—loop transistor; C1—first        comparator;    -   C2—second comparator; NOR1—first control logic circuit;        NOR2—second control logic circuit; INV—inverter; S1—first        switch; S2—second switch;    -   100—oscillator circuit; 110—current generating module;        111—current mirror circuit branch; 112—feedback loop; 120—loop        oscillation module; 121—first submodule; 122—second submodule;        200—POR circuit.

DETAILED DESCRIPTION

The core of the present invention is to provide a clock circuitcomprises an oscillator circuit and a power-on reset circuit, theoscillator circuit comprises a current generating module and a looposcillation module connected together; the current generating module isused for outputting a control current to the loop oscillation module;the loop oscillation module is used for outputting an oscillation signalwith a set frequency under action of the control current; and thepower-on reset circuit is used for providing an enabling control signalto the loop oscillation module after a power supply is powered on; thepower-on reset circuit is connected to the loop oscillation module. Inthe present invention, the power-on reset circuit is only connected withthe loop oscillation module, thus during a power-on process of the powersupply, all nodes of the current generating module are gradually setwith power-on of the power supply, thus a circuit setting time of thecurrent generating module are comprised in a time for releasing anenable control signal of the power-on reset circuit, so as to acceleratea settling time of the oscillator circuit.

A clock circuit of the present invention will be described in furtherdetail below. The specific embodiments of the present invention will befurther described in detail below with reference to the accompanyingdrawings. It should be noted that, in the following specificembodiments, when describing the embodiments of the present invention indetail, in order to clearly represent the structure of the presentinvention and facilitate the description, the structures in theaccompanying drawings are not drawn according to the general scale, andthe Partial enlargement, deformation and simplification of processingare shown, therefore, it should be avoided to interpret this as alimitation of the present invention.

In the interest of clarity, not all features of an actual embodiment aredescribed. In the following description, well-known functions orconstructions are not described in detail since they would obscure theinvention with unnecessary detail. It should be recognized that in thedevelopment of any actual embodiment, a great deal of implementationdetail must be made to achieve the developer's specific goals, such aschanging from one embodiment to another in accordance withsystem-related or business-related constraints. Additionally, it shouldbe appreciated that such a development effort may be complex and timeconsuming, but would be merely routine for those skilled in the art.

In order to make the objects and features of the present invention moreclearly understood, the specific embodiments of the present inventionwill be further described below with reference to the accompanyingdrawings. It should be noted that, the accompanying drawings are all ina very simplified form and use imprecise ratios, and are only used forfacilitate and clearly assist the purpose of explaining the embodimentsof the present invention.

It should be understood that, in the following description, “circuit”refers to a conductive loop formed by at least one element orsub-circuit by electrical or electromagnetic connection. When an elementor circuit is referred to as being “connected” to another element or anelement/circuit is “connected” between two nodes, it may be directlycoupled or connected to the other element or intervening elements may bepresent, and the connection between the elements may be physical,logical, or a combination thereof. In contrast, when an element isreferred to as being “directly coupled” or “directly connected” toanother element, it is meant that there are no intervening elementspresent.

Embodiment 1

This embodiment provides a clock circuit. FIG. 2 is a schematicstructural diagram of a clock circuit according to embodiment 1 of thepresent invention. As shown in FIG. 2 , the clock circuit comprises anoscillator circuit 100 and a POR circuit 200.

The oscillating circuit is used for outputting an oscillating signalwith a set frequency, and the oscillating circuit can be an RC(resistance-capacitor) oscillating circuit. The oscillator circuit 100comprises a current generating module 110, a loop oscillation module 120and a switch control module, the current generating module 110 is usedfor outputting a control current to the loop oscillation module 120, andthe loop oscillation module 120 is used for outputting the oscillatingsignal with the set frequency under the action of the control current.The POR circuit 200 is connected to the loop oscillation module 120 bythe switch control module, and is enabled to provide an enable controlsignal to the loop oscillation module 120, and the current generatingmodule 110 is not affected by the POR circuit 200, thus voltages of allnodes of the current generating module 110 do not need to be set after acontrol signal of the POR circuit is released, that is, during apower-on process of a power supply, all of the nodes of the currentgenerating module is gradually set with powering on the power supply,thus a circuit setting time of the current generating module iscomprised in a time for releasing the enable control signal of apower-on reset circuit, so as to accelerate setting time of theoscillator circuit.

The current generating module 110 comprises a current mirror circuitbranch 111, a feedback loop 112 and a capacitor C. The feedback loop 112is used for generating a substantially constant current required in theoscillating circuit, and the current mirror branch circuit 111 is usedfor generating a current required for charging and discharging theoscillating circuit, and generating a periodic oscillation signal bycharging and discharging of the capacitor.

The feedback loop 112 comprises an input end, a first output end and asecond output end, the input end of the feedback loop 112 is used forproviding a voltage Vref, and the first output end and the second outputend of the feedback loop 112 are connected to the current mirror branchcircuit 111. In this embodiment, the feedback loop 112 comprises anamplifier OTA and a loop transistor M0, the amplifier OTA comprises afirst end, a second end and a third end, wherein the first end of theamplifier OTA is the input end of the feedback loop 112, which is usedfor inputting the voltage Vref, the second end of the amplifier OTA isconnected to a first end of the transistor M0 and the current mirrorbranch circuit 111 simultaneously, and the third end of the amplifierOTA is connected to a gate of the loop transistor M0. The first end ofthe loop transistor M0 is the first output end of the feedback loop 112,and a second end of the loop transistor M0 is the second output end ofthe feedback loop 112.

The current mirror branch circuit 111 comprises a first output end, asecond output end, a third output end and a fourth output end, and bothof the first output end and the second output end of the current mirrorbranch circuit are connected to the feedback loop 112, the third outputend and the fourth output end of the current mirror branch circuit areconnected to the loop oscillation module 120. Specifically, the looposcillation module 120 comprises a first end and a second end, whereinthe third output end of the current mirror branch circuit is connectedto the second end of the loop oscillation module 120, and the fourthoutput end of the current mirror branch circuit is connected to thefirst end of the loop oscillation module 120.

In this embodiment, the current mirror branch circuit 111 comprises afirst transistor M1 to a seventh transistor M7 and a resistor R.Wherein,

-   -   a first end of the first transistor M1 is a first output end of        the current mirror branch circuit, and the first end of the        first transistor M1 is connected to the first end of the loop        transistor M0; the second end of the transistor M1 is        simultaneously connected to a second end of the second        transistor M2 and a second end of the third transistor M3; a        gate of the first transistor M1 is simultaneously connected to        the first end of the first transistor M1, a gate of the second        transistor M2 and a gate of the third transistor M3; a first end        of the second transistor M2 is simultaneously connected to a        second end of the fourth transistor M4, a gate of the fourth        transistor M4 and a gate of the fifth transistor M5; a first end        of the third transistor M3 is connected to a second end of the        sixth transistor M6; a first end of the fourth transistor M4 is        simultaneously connected to a first end of the resistor R, a        first end of the fifth transistor M5 and a first end of the        capacitor C; a second end of the fifth transistor M5 is        connected to a first end of the seventh transistor M7; a first        end of the sixth transistor M6 is a fourth output end of the        current mirror branch circuit, which is simultaneously connected        to a second end of the seventh transistor M7, a second end of        the capacitor and the loop Oscillation module 120; a gate of the        sixth transistor M6 is used as a third output end of the current        mirror branch circuit, which is simultaneously connected to a        gate of the seventh transistor M7 and the loop oscillation        module 120. The sixth transistor M6 is used for controlling        turn-on or turn-off of the third transistor M3, and the seventh        transistor M7 is used for controlling turn-on or turn-off of the        fifth transistor M5.

In this embodiment, the first transistor M1 to the third transistor M3are, for example, the same size, and the fourth transistor M4 and thefifth transistor M5 are, for example, the same size, thus currents ofthe first transistor M1 to the fifth transistor M5 in the current mirrorbranch circuit are the same. Under an action of the feedback loop 112, avoltage on the first end of the amplifier OTA is equal to the voltage onthe second end thereof, so as to form a basic reference current (Iref)flowing through the resistor R, and Iref=Vref/R. Under action of thefirst transistor M1 to the fifth transistor M5, if a current flowsthrough the third transistor M3 and the fifth transistor M5, currentsflowing through the third transistor M3 and the fifth transistor M5 arealso the same, which are Iref, and whether currents flow through thethird transistor M3 and the fifth transistor M5, is respectively relatedto whether the sixth transistor M6 and the seventh transistor M7 areturned on. Of course, in other embodiments, sizes of the firsttransistor M1 to the fifth transistor M5 can be set according torequirements.

The loop oscillation module 120 comprises a first sub-module 121 and asecond sub-module 122 connected in series, the switch control module isconnected between the first sub-module 121 and the second sub-module122, and a fourth output end of the current mirror branch circuit 111 isconnected to the first sub-module 121, and a third output end of thecurrent mirror branch circuit 111 is connected to the second sub-module122. The first sub-module 121 comprises a plurality of comparators andcontrol logic circuits. In this embodiment, the first sub-module 121comprises comparators (a first comparator C1 and a second comparator C2)and two control logic circuits (a first control logic circuit NOR1 and asecond control logic circuit NOR2). a first input end of the firstcomparator C1 is simultaneously connected to the fourth output end ofthe current mirror branch circuit and a second input end of the secondcomparator C2; a second input end of the first comparator C1 isfloating. The first control logic circuit NOR1 and the second controllogic circuit NOR2 are, for example, NAND gates, and both the firstcontrol logic circuit NOR1 and the second control logic circuit NOR2comprise a first input end, a second input end and an output end, theoutput signal of the first control logic circuit NOR1 is used forcontrolling charging and discharging of the current generating module110, and by controlling charging and discharging currents, a capacitancevalue, and input a voltage of the comparator, a period and a duty cycleof the oscillating signal of the oscillating circuit are determined.

A first input end of the first control logic circuit NOR1 is connectedto an output end of the first comparator; a second input end of thefirst control logic circuit NOR1 is connected to an output end of thesecond control logic circuit; an output end of the first control logiccircuit NOR1 is simultaneously connected to the switch control moduleand a first input end of the second control logic circuit NOR2. A firstinput end of the second comparator C2 is floating, and an output end ofthe second comparator C2 is connected to a second input end of thesecond control logic circuit NOR2. The loop oscillation module 120 isused for limiting a highest voltage and a lowest voltage of the basicoscillation signal generated by the oscillator circuit by thecomparator, and generating a periodic oscillation signal by controllingcharging and discharging of the oscillator circuit.

The second sub-module 122 comprises, for example, a plurality ofinverters. In this embodiment, the second sub-module 122 comprises, forexample, an inverter INV, and an input end of the inverter INV isconnected to the switch control module, an output end of the inverterINV is connected to a third output end of the current mirror branchcircuit. The output end of the inverter INV is used as an output end ofthe oscillator circuit 100.

The switch control module is used for keeping the loop oscillationmodule 120 and the current generating module 110 resetting before thepower supply is powered on, and keeping a loop of the loop oscillationmodule 120 working normally after the power supply is powered on. Theswitch control module comprises, for example, a first switch S1 and asecond switch S2, and a first end of the first switch S1 is connected tothe output end of the first control logic circuit NOR1 and the PORcircuit 200 simultaneously; a second end of the first switch S1 issimultaneously connected to the first end of the second switch and theinput end of the inverter INV; a second end of the second switch S2 isgrounded and connected to the POR circuit 200 simultaneously. Since thefirst switch S1 and the second switch S2 are controlled by two oppositesignals from the same POR circuit 200, states of the first switch S1 andthe second switch S2 are different at each moment, that is, for thefirst switch S1 and the second switch S2, at each moment, one of themmust be turned off, and the other one must be turned on.

As shown in FIG. 2 , when the first switch S1 is turned off and thesecond switch S2 is turned on, since a circuit of the loop oscillationmodule 120 is in an open-loop state, all of the nodes of the oscillatorcircuit maintain a reset state stably.

When the first switch S1 is turned off and the second switch S2 isturned on, a power-on process is entered first. Meanwhile, theoscillator circuit is started from a reset state, the enable controlsignal is not released by the POR circuit 200, the loop oscillationmodule 120 is in the open-loop state, and the voltages of all of thenodes of the loop oscillation module 120 remain unchanged, thus all ofthe nodes of the loop oscillation module 120 are always in the resetstate. Specifically, the first end of the second switch S2 is at a lowvoltage, and after applying the low voltage to the inverter INV, avoltage at the third output end of the current generating module 110 isa high voltage, the sixth transistor M6 is turned off, the seventhtransistor M7 is turned on, thus the fifth transistor M5 is turned on,and the current flowing through the fifth transistor M5 is Iref. Underactions of the seventh transistor M7 and the fifth transistor M5, avoltage of the fourth output end of the current generating module 110 ispulled to a low voltage, and a voltage of the fourth output end of thecurrent generating module 110 is compared with the first comparator C1and the second comparator C2, and a low voltage is output at the outputend of the first comparator, and a high voltage is output at the outputend of the second comparator, and finally after applying to the firstcontrol logic circuit and the second control logic circuit, a highvoltage is output at the output end of the first control logic circuit,and a low voltage is output at the output end of the second controllogic circuit.

After the power supply is turned on, before the enable control signal isreleased by the POR circuit 200, the voltages of all of the nodes of theoscillator circuit 100 remain unchanged, and as the power supply isturned on, a voltage of each of the nodes in the current generatingmodule 110 are increased, and finally a stable current path is formed.

After the POR circuit 200 is powered on, the enable control signal isgenerated after a voltage of the power supply is stable, that is, theenable control signal is released by the POR circuit 200 automatically,and then under an action of the enable control signal, the switchcontrol module will be changed into a working state automatically, thenthe oscillation loop is closed, thus the oscillation signal is generatedstably, so as to start the clock circuit quickly. Meanwhile, under theaction of the enable control signal, a switch state of the switchcontrol module is changed, that is, the first switch S1 is turned on,the second switch S2 is turned off, under an action of the controlsignal output by the loop oscillation module 120, the capacitor C ischarged or discharged by the current mirror branch circuit to form aperiodic oscillating clock signal whose high and low levels areconstantly changing, thus the clock circuit only needs to oscillate oncein the oscillating circuit to set up completely, and the setting time isshort.

Specific, after the enable control signal is released by the POR circuit200, since the first end of the second switch S2 is affected by avoltage at a node A, a voltage at the first end of the second switch S2is changed from a low voltage to a high voltage, after the high voltageis applied to the inverter INV, a voltage at the third output end of thecurrent generating module 110 is a low voltage, meanwhile, the sixthtransistor M6 is turned on, the seventh transistor M7 is turned off,thus the third transistor M3 and the sixth transistor M6 are turned on,then the capacitor is charged, and a voltage V1 on the capacitor isgradually increased from a low voltage.

When the voltage V1 is lower than a voltage VL of the first input end ofthe second comparator (that is, V1<VL), the capacitor C is keptcharging, thus the voltage V1 becomes larger and larger until thevoltage V1 is larger than a voltage of the first input end of the secondcomparator, a comparison result of the second comparator C2 is changed,meanwhile, a high voltage is output at the output end of the firstcontrol logic circuit NOR1, and a low voltage is output at the outputend of the second control logic circuit NOR2, an output end voltage ofthe second comparator C2 is changed from a high voltage to a lowvoltage, and the capacitor C is kept charging, thus the voltage V1 iskept increasing,

When the voltage V1 is larger than an input voltage VH of the secondinput end of the first comparator (V1>VH), a comparison result of thefirst comparator is changed. meanwhile, an output end voltage of thefirst comparator is changed from a low voltage to a high voltage, andthe output end voltage of the second comparator is changed from a lowvoltage to a high voltage, a voltage of the first end of the secondswitch is changed from a low voltage to a high voltage, a voltage at thethird output end of the current mirror branch circuit is changed from alow voltage to a high voltage, thus the sixth transistor M6 is turnedoff, and the seventh transistor M7 is turned on, then the capacitor isdischarged, and a voltage of the fourth output end of the current mirrorbranch circuit is dropped. When VL<V1<VH, the comparison result of thefirst comparator is changed, meanwhile, the voltage of the output end ofthe first comparator is changed from a high voltage to a low voltage,and a high voltage is output at the output of the second control logiccircuit, a low voltage is output at the output of the first controllogic circuit, and the capacitor is kept discharging.

Before the voltage V1 is decreased to the voltage VL of the first inputend of the second comparator, the node voltage state of the looposcillation module remains unchanged. When the voltage V1 is lower thanthe voltage VL of the first input end of the second comparator, thecomparison result of the second comparator is changed, a high voltage isoutput at the output end of the second comparator, meanwhile, a voltageat the output end of the second control logic circuit is changed from ahigh voltage to a low voltage, and a voltage at the output end of thefirst control logic circuit is changed from a low voltage to a highvoltage, the voltage at the node A is changed from a low voltage to ahigh voltage, the voltage at the third output end of the current mirrorbranch circuit is changed from a high voltage to a low voltage, thesixth transistor M6 is turned on, the seventh transistor M7 is turnedoff, and the capacitor C is in a charging mode. It can be seen that aclock of the voltage V1 is limited between the input voltage VH of thesecond input end of the first comparator C1 and the voltage VL of thefirst input end of the second comparator C2, and the voltage at thethird output end of the current mirror branch circuit is a square wavethat is constantly changing between the high voltage and the firstvoltage, a time at the high voltage thereof is equal to a discharge timeof the capacitor, and a time at the low level is equal to a charge timeof the capacitor. After the enable control signal is released by the PORcircuit 200, the capacitor can keep outputting a stable periodic squarewave after only one charging cycle, and a circuit startup time is veryshort after the power supply is turned on.

Embodiment 2

This embodiment provides a clock circuit. A difference between thisembodiment and the first embodiment is that: as shown in FIG. 3 , theoscillator circuit 100 comprises the current generating module 110 andthe loop oscillation module 120, and the POR circuit 200 is directlyconnected to the loop oscillation module 120, further, the looposcillation module 120 comprises a first sub-module 121 and a secondsub-module 122 connected in series, and the POR circuit 200 is connectedto the first sub-module 121.

Specifically, there is a node B1 between the output end of the firstcomparator and the first input end of the first control logic circuitNOR1, and there is a node B2 between the output end of the secondcomparator C2 and the second input ends of the second control logiccircuit NOR2, the first output end of the POR circuit 200 is connectedat the node B1, and the second output end of the POR circuit 200 isconnected at the node B2. The voltages of all of the nodes of thecurrent generating module 110 can be set simultaneously as node voltagesof the loop oscillation module 120 connected to the POR circuit 200 areset, thus a stable time of the oscillator circuit is only a timerequired for releasing the POR circuit, so as to accelerate the settlingtime of the oscillator circuit.

To sum up, in the oscillator circuit of the clock circuit provided bythe present invention, the current generating module will not be locked,and only the loop oscillation module can be deadlocked. Then, thecurrent generating module cannot be controlled by the enable controlsignal of the POR circuit, during the power-on process of the powersupply, all of the nodes of the current generating module are graduallyset with the power-on of the power supply. thereby the setting time ofthe current generating module is comprised in a release time of theenable control signal of the POR circuit. within the release time of theenable control signal, so as to accelerate the settling time of theoscillator circuit.

In addition, it should be noted that, unless otherwise specified orpointed out, the descriptions of the terms “first”, “second”, etc. inthe specification are only used for distinguish various components,elements, steps, etc. in the specification, rather than to indicate thelogical relationship or sequence relationship between variouscomponents, elements, steps, etc.

The above descriptions are only the preferred embodiments of the presentinvention, and the described embodiments are not used to limit the scopeof patent protection of the present invention. Therefore, any equivalentstructural changes made using the contents of the description anddrawings of the present invention should be included of the samereasoning. Within the protection scope of the appended claims of thepresent invention.

What is claimed is:
 1. A clock circuit comprises an oscillator circuitand a power-on reset circuit, wherein the oscillator circuit comprises acurrent generating module and a loop oscillation module connectedtogether; the current generating module is used for outputting a controlcurrent to the loop oscillation module; the loop oscillation module isused for outputting an oscillation signal with a set frequency underaction of the control current; and the power-on reset circuit is usedfor providing an enabling control signal to the loop oscillation moduleafter a power supply is powered on; the power-on reset circuit isconnected to the loop oscillation module.
 2. The clock circuit of claim1, wherein the loop oscillation module comprises a first sub-module anda second sub-module, the first sub-module and the second sub-module areconnected in series, and the first sub-module comprises a plurality ofcomparators and control logic circuits.
 3. The clock circuit of claim 2,wherein the first sub-module comprises a first comparator, a secondcomparator, a first control logic circuit and a second control logiccircuit; a first input end of the first comparator is simultaneouslyconnected to a current mirror circuit branch and a second input end ofthe second comparator; a second input end of the first comparator isfloating; a first input end of the first control logic circuit isconnected to an output end of the first comparator; a second input endof the first control logic circuit is connected to an output end of thesecond control logic circuit; an output end of the first control logiccircuit is simultaneously connected to a switch control module and thefirst input end of the second control logic circuit; a first input endof the second comparator is floating, and an output end of the secondcomparator is connected to a second input end of the second controllogic circuit.
 4. The clock circuit of claim 3, wherein the power-onreset circuit comprises a first output end and a second output end; thefirst output end of the power-on reset circuit is simultaneouslyconnected to the first input end of the first control logic circuit andthe output end of the first comparator; and the second output end of thepower-on reset circuit is simultaneously connected to the output end ofthe second comparator and the second input end of the second controllogic circuit.
 5. The clock circuit of claim 3, wherein the oscillatorcircuit further comprises the switch control module, and the power-onreset circuit is connected to the loop oscillation module by the switchcontrol module.
 6. The clock circuit of claim 5, wherein the switchcontrol module is connected between the first sub-module and the secondsub-module.
 7. The clock circuit of claim 6, wherein the switch controlmodule comprises a first switch and a second switch; a first end of thefirst switch is simultaneously connected to the output end of the firstcontrol logic circuit and the power-on reset circuit; a second end ofthe first switch is simultaneously connected to a first end of thesecond switch and the input end of the second sub-module; a second endof the second switch is grounded and connected to the power-on resetcircuit simultaneously; wherein, the first switch and the second switchare selectively turned on.
 8. The clock circuit of claim 2, wherein afirst end of the second sub-module is connected to the switch controlmodule, and a second end of the second sub-module is connected to thecurrent mirror branch circuit and used as an output end of theoscillator circuit.
 9. The clock circuit of claim 8, wherein the secondsub-module comprises a plurality of inverters.
 10. The clock circuit ofclaim 1, wherein the current generating module comprises a currentmirror circuit branch, a feedback loop and a capacitor, the feedbackloop is used for generating a substantially constant current required inthe oscillator circuit, and the current mirror branch circuit is usedfor generating a current required for charging and discharging of theoscillator circuit and generating a periodic oscillation signal bycharging and discharging of the capacitor.